The present invention relates to the field of programmable logic devices, and more particularly, to programmable logic devices having highly flexible and efficient logic elements.
Logic devices and methods of their operation are well known to those of skill in the art. Programmable logic devices have found particularly wide application as a result of their combined low up-front cost and versatility to the user.
Altera's FLEX.RTM. and MAX.RTM. lines of programmable logic are among the most advanced and successful programmable logic devices. In the FLEX.RTM. 8000 logic devices, for example, a large matrix of logic elements (LEs), also known as logic cells (LCells) is utilized. In one commercial embodiment of such devices, each logic element effectively includes a 4-input logic block for performance of combinational logic (e.g., AND, OR, NOT, XOR, NAND, NOR, and many others) and a register that provides sequential logic features.
The logic elements are arranged in groups of, for example, eight to form larger logic array blocks (LABs). The LABs contain, among other things, a local interconnection structure. The various LABs are arranged in a two-dimensional array, with the various LABs connectable to each other and to I/O pins of the device though continuous lines that run the entire length/width of the device. These lines are referred to as row interconnect and column interconnect or collectively as "global" interconnect lines. In Altera's line of production these may include what are referred to as "Horizontal FastTracks.TM." and "Vertical FastTracks.TM.." Further details on the FLEX and MAX products are provided in Altera's databook.
These logic devices have met with substantial success and are considered pioneering in the area of programmable logic. While pioneering in the industry, certain limitations still remain. Notably, in applications that use currently available devices, some of the resources of the device may be wasted when performing certain functions.
For example, the resources of a 4-input logic element are not all used when performing a 3-input logic functions. Consequently, the remaining resources (i.e., one of the inputs and the unused logic functionality) are wasted. Currently available devices do not allow the results of more than one logic function to be provided by a single logic element.
In some commercial embodiments, lookup tables are used to provide the logic functions. Each logic element has one lookup table that provides an output based on the value on the logic element's inputs. Though the lookup table can perform combinational logic for the number of inputs the logic element provides, (e.g., a 4-input lookup table for a 4-input logic element,) the logic element is actually comprised of a number of smaller lookup tables (e.g., two 3-input lookup tables, one or both of which may be made up of two 2-input lookup tables.) Thus, if a logic element is used to perform a logic function for only three inputs, the other 3-input logic function is unused and wasted. Although illustrated herein by reference to a lookup table, other types of logic functions used in logic elements may be similarly wasted.
Further, often a logic element is used for rebuffering and routing of signals. In this scenario, only one of the inputs to the logic element is used, while the logic functions and remaining inputs of the logic element go unused. Again, this is a waste of inputs and logic resources on the logic device.
Finally, though existing devices provide for a carry function from one logic element to adjacent logic elements, these devices have no provisions for routing the carry function to the interconnect system of the PLD.
For at least the above reasons, a PLD which makes more efficient use of logic resources and provides greater interconnect flexibility is needed.